https://www.chenshaowen.com/en/tags/operations/Recent content in Operations on Shaowen Chen's WebsiteHugo -- gohugo.ioen©2016 - {year}, All Rights Reserved.Sat, 22 Aug 2026 00:00:00 +0000weeklyhttps://www.chenshaowen.com/en/blog/rdma-ops.htmlSat, 22 Aug 2026 00:00:00 +0000Sat, 22 Aug 2026 00:00:00 +0000https://www.chenshaowen.com/en/blog/rdma-ops.html1. RoCE 1.1 Connectivity Requirements RDMA requires the same class of network end to end, for example the same /16 subnet. Single switch. RoCE: host NIC ── Ethernet switch (PFC) ── peer NIC Multiple switches. RoCE: host NIC ── Leaf ── Spine ── Leaf ── peer NIC When there are multiple hops, note:微信公众号RDMARoCEInfiniBandNetworkOperationsHigh Performance Computinghttps://www.chenshaowen.com/en/blog/ops-storage-knowledge.htmlSat, 15 Aug 2026 00:00:00 +0000Sat, 15 Aug 2026 00:00:00 +0000https://www.chenshaowen.com/en/blog/ops-storage-knowledge.html1 Volatile Memory 1.1 REG REG (Register) is a storage unit inside the CPU, sitting right next to the arithmetic unit — the fastest and smallest level of the storage hierarchy. General-purpose registers (RAX/RBX/RDI on x86, and so on) take part directly in instruction execution, with access latency around 0.2–0.5 ns (roughly one clock cycle), lost on power loss, and typically only tens to hundreds of bytes.微信公众号OperationsStorageSystemsArchitecture