1. What the Image Tag Suffixes Mean base/cuda: includes the CUDA runtime runtime: builds on base, adding the CUDA math libraries and the NCCL and cuDNN runtimes devel: builds on runtime, adding headers and the development tools used to build CUDA images; particularly useful for multi-stage builds cuddn: builds on the above, adding the cuDNN neural network acceleration library

1. Installing conda 1 2 3 wget https://repo.anaconda.com/miniconda/Miniconda3-latest-Linux-x86_64.sh bash Miniconda3-latest-Linux-x86_64.sh rm -rf Miniconda3-latest-Linux-x86_64.sh However, Miniconda cannot be used for free at large-scale commercial deployments, so you can use Miniforge as a drop-in alternative. 1 2 wget "https://github.com/conda-forge/miniforge/releases/latest/download/Miniforge3-$(uname)-$(uname -m).sh" bash Miniforge3-$(uname)-$(uname -m).sh 2. Changing the default configuration 2.1 Initializing the Shell Without initialization, activating an environment reports CondaError: Run 'conda init' before 'conda activate'.

1. Introduction to Volcano Volcano is a Kubernetes-based resource scheduling system open-sourced by Huawei. Compared with the native scheduler, its notable features are: Supports gang scheduling Scheduling batch jobs easily runs into deadlock: for example, two jobs each need 10 Pods running simultaneously to start. When both jobs are submitted at the same time, it is possible that only part of the Pods of each are scheduled, so neither job can run properly and they wait on each other.

1. What Is npu-smi npu-smi is a command-line tool provided by Huawei, purpose-built for managing and monitoring the status and performance of Huawei Ascend series Neural Processing Units (NPUs), similar to NVIDIA’s nvidia-smi. 2. Meaning of npu-smi Fields 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 npu-smi info +------------------------------------------------------------------------------------------------+ | npu-smi 23.

I have been studying the infrastructure around model training lately, and I found that AI chip interconnect topology determines the scheduling and resource allocation of training cluster jobs. So I spent a little time putting together the common AI chip interconnect solutions. 1. Point-to-Point Interconnect In a traditional PCIe system, data transfer between AI chips goes over PCIe, which cannot meet the demands of large-scale data transfer.